1. Field of the Invention
The present invention relates in general to a power delivery analysis system and in particular to a power delivery analysis system for server designs consisting of several packaging hierarchies.
2. Description of Background
It is often desirable in the microelectronics industry to be able to implement physical solutions in as little time as possible for coping with new market opportunities and/or emerging problems. Computer-provided simulations are often used to predict the behaviors of to-be-manufactured electrical circuits or other like systems. This is preferably done before the electrical circuits are finalized so that design errors may be corrected and design parameters may be optimized prior mass production.
Computers and software simulators can be used for obtaining fairly accurate predictions of the analog behaviors of linear circuitry. Other examples of analog-behavior simulators include HSPICE® (available from Avant! Corp. California), SPICE-3® (available from Berkeley University of California), SPECTRE® (available from Cadence Corp. of California), ACES® (Adaptively Controlled Engine Simulator), and ITA® (Interactive Timing Analysis engine). These simulators and/or simulation engines are not to be confused with digital-behavior simulators such as VHDL which predict behavior of gate-level and lower-resolution hardware descriptions (e.g., register transfer level) in the digital realm rather than at the finer resolution of transistor-level signals and in the analog realm.
SPICE-like simulations can provide fairly accurate predictions of how corresponding circuits will behave when actually built. The predictions are preferably made not only for individual sub-circuits but also for whole systems (e.g., whole integrated circuits) so that system wide problems relating to noise and the like can be uncovered and dealt with.
However, simulation of whole systems becomes more difficult and problematic as the industry continues its relentless trek of scaling down to smaller and smaller device geometries as is predicted by Moore Law and of cramming more interconnected components into a system. An example of such down scaling is the recent shift from micron-sized channels toward deep submicron sized transistor lengths. Because of this, circuit designers are able to cram exponentially larger numbers of basic components or ‘elements’ (e. g., transistors, diodes, capacitors) into a given integrated circuit (IC) or other such, mass-producible device.
Due to the shortened time-to-market pressures in the industry, the designers of these mass-producible systems (e.g., IC's) want the makers of pre-fabrication SPICE-like simulators to come up with new ways for quickly and accurately predicting the system-wide behaviors of these exponentially more dense and more complex, interconnected system designs.
Accordingly what is needed is a method of providing end users with the capability under one system of performing fully flattened model simulations.